Semiconductor circuit and method of controlling the same

ABSTRACT

An object of the invention, in a semiconductor circuit or, more particularly, in an LSI on which a DRAM and a logic circuit are merged, is to decrease the frequency of times of refreshing operations to thereby achieve both reduction in power consumption and prevention of deterioration in the performance of the logic circuit caused by an increase in the memory access time due to contention between refresh and DRAM access of the logic circuit. 
     To achieve the object, the refreshing is done only for rows storing the data used by the logic portion. 
     Further, arbitrary data for which periods from being written in to being read out are overlapping or close to each other are allocated to the same row of the DRAM so as to be stored thereon, and the row is refreshed only during the period of time that the data stored thereon is live.

TECHNICAL FIELD

The invention relates to a semiconductor circuit and a control methodthereof and more particularly to a semiconductor circuit and a controlmethod thereof wherein the interval between refreshing operations of aDRAM is prolonged.

BACKGROUND ART

With the progress in the integration of semiconductors, it has becomepossible to integrate a processor, a memory, or other circuit onto onechip. Further, with the progress in the technology of processes enablinga logic circuit such as a processor and DRAM (Dynamic RAM) to be mergedon one chip, it has become possible to implement DRAM on a memory.

Each memory cell of DRAM is small, and made of a capacitor. Theiradvantage over the implementing of SRAM (Static RAM) is that the chiparea can be greatly reduced. On the other hand, they bring such adisadvantage in that the electric charge stored thereon as datadischarges with the passage of time and, hence, the data is lost.Therefore, it is necessary to make an operation to keep data from beinglost. The memory cells of DRAM in general are arranged in a matrixarray. The data stored in the memory cells are read out all at once foreach row, detected by a sense amplifier, and the values of the data readout are written into the memory cells from which the data were read out.Such a sequence of operations is called “refresh”.

During the refreshing operation, the DRAM does not accept any access toitself. In the normal mode which allows read/write from outside theDRAM, the refreshing operation is executed by a DRAM controller outsidethe DRAM, but in a sleeping mode such as when backed up by battery, therefreshing operation is performed by a refresh controller inside theDRAM LSI. In the sleeping mode, any read/write access from outside theDRAM is not accepted.

Here, some problems arise when the DRAM and logic circuit are merged onthe same LSI.

Merged DRAM/logic LSIs, however, have some disadvantages such that theDRAM portion of merged DRAM/logic LSIs might suffer from shorter dataretention time. Heat and noise dissipated by the logic portion on thesame chip could be harmful to the data retention time of the one-tipDRAM. When the ambient temperature rises, for example, from 25° C. to70° C., the leakage current of the charge stored on the memory cell ofthe DRAM is increased by 30 fold and, hence, it becomes necessary tocarry out the refreshing operation 30 times more frequently (Ito, “VLSIMemory Design”, Baifukan). In a system using conventional DRAM,refreshing operations are made at short intervals assuming the worstoperating environmental conditions. Therefore, under normal temperatureconditions, refreshing operations are being made at a great frequency.

There is great variation of the data retention time among the memorycells of DRAM and few memory cells have short data retention times(Iwata et al. “Circuit Techniques for Super Low Retention Current DRAM”,Technical Report of Institute of Electronics, Information, andCommunication Engineers, ICD 95-50). However, refreshing operations arebeing made at the same cycle time for all of the rows. This means thatrefreshing operations are being made at a greater frequency than isneeded for many of the rows, often including no memory cells that have asmall actual capacity in terms of data retention time.

Further, all of the rows are refreshed whether the data held in DRAM arenecessary for the logic circuit or not. In reality, only necessary dataneed be held in memory and, hence, unnecessary data need not berefreshed.

Such excessive refreshing invites wasteful power consumption.

Under these circumstances, means for decreasing the frequency ofrefreshing operations are being investigated. As a technique to decreasepower consumption in the data retention mode of a conventional DRAM,there is a method 1 in which self-refreshing is conducted at arefreshing cycle time corresponding to temperature (Japanese PatentLaid-Open No. 6-215561). Further, as a technique to decrease powerconsumption in the normal mode of a conventional DRAM, there is a method2 in which a control for the power supply and the decision as to whethera refreshing operation should be carried out is executed according to aflag set up in each memory area (Japanese Patent Laid-Open No. 5-324140,U.S. Pat. No. 5,469,559).

However, in Method 1 above, since the refreshing cycle time in thenormal mode is adjusted to the memory cell having the shortest dataretention time in the DRAM, there still remains the unresolved problemof power consumption in the normal mode. Further, Method 2 does not copewith variations in the data retention time.

What is more important is that the merged DRAM/logic LSI has aconnection at a wide memory band width to achieve highly improvedprocessing performance of the logic portion. In such an LSI, therearises a problem of conflict between refresh and access to the DRAM madeby the logic circuit, thereby prolonging the time required for DRAMaccess and, hence, the processing performance of the logic circuit isdeteriorated. This is a serious problem, comparable with the problem ofachieving reduction in power consumption.

The first object of the present invention, in a semiconductor circuitor, more particularly, in an LSI on which a DRAM and a logic circuit aremerged, is to decrease the number of refreshing operations by refreshingonly the rows storing necessary data, and thereby achieve both reductionin power consumption and prevention of deterioration in the performanceof the logic circuit caused by an increase in the access time due to theconfliction between refresh and access to the DRAM.

A second object of the invention is to determine the rows storing datathereon according to the degree of importance of the data to, thereby,ensure saving important data without excessively shortening the refreshcycle time.

A third object of the invention is to have refreshing operations carriedout at suitable cycle time in conformity with the temperatures tothereby achieve both reduction in power consumption and prevention ofdeterioration in the processing performance of the logic circuit.

DISCLOSURE OF THE INVENTION

In order to achieve the first object, the invention, in a control methodof a merged DRAM/logic LSI, is characterized by comprising the steps ofdisposing data, which are combined so that the number of the rowsstoring data thereon may be reduced, on each of the rows of the DRAM andrefreshing each of the rows having data stored thereon.

Another method to achieve the first object, in a control method of amerged DRAM/logic LSI, is characterized by comprising the steps ofdisposing arbitrary data of which periods from being written in to beingread out are overlapping or close to each other are disposed on the samerow of the DRAM and refreshing the row only during the time period fromthe writing in of the data at the first to the reading out thereof atthe end.

A method to achieve the first and the second objects, in a controlmethod of a merged DRAM/logic LSI, comprises the steps of obtaining thememory capacity required by an application using DRAM and storing datain DRAM in order from a row having a longer data retention time, withreference made to a table storing previously obtained data retentiontime of each row of DRAM, and setting a refreshing cycle adapted to therow whose data retention time is the shortest of the rows storing datathereon.

In this method, data may be disposed, when it is stored in the DRAM, onspecific rows in accordance with the importance of the data.

A method to achieve the third object, in each of the above methods, ischaracterized by comprising the step of detecting the temperature of thesemiconductor circuit and setting the refreshing cycle time of the DRAMaccording on the temperature.

A semiconductor circuit to achieve the first object is characterized bycomprising means for disposing data, which are combined so that thenumber of the rows storing the data thereon may be reduced, on each ofthe rows of the DRAM and means for refreshing each of the rows havingthe data stored thereon.

Another semiconductor circuit which has achieved the first object ischaracterized by comprising means for disposing arbitrary data of whichperiods from being written in to being read out are overlapping or closeto each other on the same row of DRAM, and means for refreshing the rowonly during the time period from the writing in of the data to thereading out thereof at the end.

A semiconductor circuit which has achieved the first and the secondobjects is characterized by comprising means for obtaining the memorycapacity required by an application using DRAM and storing data in theDRAM in an order starting from a row having longer data retention time,with reference made to a table storing the previously obtained dataretention time of each row of DRAM, and means for setting a refreshingcycle time adapted to the row whose data retention time is the shortestof the rows storing data thereon.

In this semiconductor circuit, there may be provided means for disposingdata, when it is stored in the DRAM, on specific rows in accordance withthe degree of importance of the data.

A semiconductor circuit which has achieved the third object, in each ofthe above semiconductor circuits, is characterized by comprising meansfor detecting the temperature of the semiconductor circuit and settingthe refreshing cycle of the DRAM according to the temperature.

According to this invention, the following meritorious effects can beobtained:

(1) Since only the rows storing necessary data are refreshed, the numberof refreshing operations can be decreased and, hence, reduction in powerconsumption and prevention of deterioration in the processingperformance of the logic circuit caused by contention between refreshand DRAM access can be attained.

(2) Since the rows on which data are written are determined according tothe degree of importance of the stored data, the need for excessivelyshortening the refreshing cycle can be eliminated and, hence, reductionin power consumption and prevention of deterioration in the processingperformance of the logic circuit caused by contention between refreshand DRAM access can be attained.

(3) Since the refreshing cycle is set according to temperature, the needfor excessively shortening the refreshing cycle can be eliminated and,hence, reduction in power consumption and prevention of deterioration inthe processing performance of the logic circuit caused by contentionbetween refresh and DRAM access can be attained.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing the general configuration of aninformation processing apparatus to which a semiconductor circuit of theinvention is applied.

FIG. 2 is a block diagram showing an internal configuration of the mainmemory unit 4 shown in FIG. 1.

FIG. 3 is a block diagram showing an internal configuration of the DRAM7.

FIG. 4(a) is a diagram showing the relationship between stored positionsof data and rows before optimization and FIG. 4(b) is a diagram showingthe relationship between stored positions of data and rows afteroptimization.

FIG. 5 is a functional diagram showing the principle of memoryallocation made by a compiler in a first embodiment.

FIG. 6 is a functional diagram showing the principle of memoryallocation made by an operating system in the first embodiment.

FIG. 7 is an explanatory drawing of a second embodiment, of which (a) isa graph showing lifetimes of data in a DRAM, (b) is an explanatorydrawing of a case where data are disposed without taking the lifetimesof the data into consideration, (c) is a graph showing lifetimes of datadisposed on each row, (d) is an explanatory drawing of a case where datawhose lifetimes are similar are disposed on the same row and stored inthe DRAM, and (e) is a graph showing the lifetimes of data on each ofthe rows after the disposition of the data A-H is optimized.

FIG. 8 is a functional diagram showing the principle of memoryallocation made by a compiler in the second embodiment.

FIG. 9 is a functional diagram showing the principle of memoryallocation made by an operating system in the second embodiment.

FIG. 10 is a block diagram of an embodiment where a data retention timestoring table is provided in a third embodiment.

FIG. 11 is a functional diagram showing the principle of memoryallocation made by a compiler in the third embodiment.

FIG. 12 is a functional diagram showing the principle of memoryallocation made by an operating system in the third embodiment.

FIG. 13 is a functional diagram showing the principle of memoryallocation made by a compiler in a fourth embodiment.

FIG. 14 is a block diagram of a fifth embodiment provided with a meansfor detecting temperature and a means for controlling the refreshingcycle time.

BEST MODE FOR CARRYING OUT THE INVENTION

FIG. 1 is a block diagram showing a general configuration of aninformation processing apparatus to which the semiconductor circuit ofthe invention is applied. A processor 1, a ROM 3, a main memory unit 4,a temperature detection means 5, an I/O (input/output interface) 6, andthe like are connected by a bus 2. The main memory unit 4 includes aDRAM 7 for storing data, a DRAM controller 8 for controlling write andread operations on the DRAM 7, and a data retention time storing means 9for storing data retention times of each of the rows in the DRAM 7.Here, a logic portion 33 is constituted of non-memory circuits such aslogic circuits, including the processor 1, the I/O 6, and the like.

FIG. 2 is a block diagram showing an internal configuration of the mainmemory unit 4 shown in FIG. 1. The DRAM controller 8 within the mainmemory unit 4 includes a row address generating means 10 for generatingthe row address of the row of the DRAM 7, a timer 11 for deciding thetiming of generation of the row address, and a row flag storing portion12 for setting the row as the object of refreshing in the DRAM 7. TheDRAM 7 is connected to the bus 2 through the interface (i/f) 13.

One DRAM controller 8 is implemented within the chip of a mergedDRAM/logic LSI and performs control of the refreshing operation and thelike at all times irrespective of the operation mode of the DRAM.

In a conventional system in which a logic circuit and a DRAM areconnected with each other on a print circuit board, there are circuitsfor separately performing refreshing both outside and inside the DRAM,and they may operate in different cycles depending on the modes (normalmode/sleep mode) of the DRAM. This is the point in which it is differentfrom the DRAM controller in the merged DRAM/logic LSI.

Every time a predetermined time period is counted out by the timer 11being a component of the DRAM controller 8, the row address generatingmeans 10 outputs a refresh address to thereby update the address of therow. The row flag 12 includes the flags corresponding to each of therows in the DRAM. The DRAM controller 8 refers to the value of the flagcorresponding to the row indicated by the row address generating means10 every time a predetermined time period is counted out by the timer11, and carries out a refreshing operation only when the value of theflag is set so that a refreshing operation should be made and,otherwise, it makes no operation. As the predetermined time period, thetime obtained by dividing the refreshing cycle time by the number of therows, for example, is used.

The DRAM controller 8 also has a function to coordinate the contentionmade between access to the DRAM through the bus 2 and a refreshingoperation. Incidentally, the processor 1 and the DRAM 7 within the mainmemory unit 4 may have a path to connect with each other not by way ofthe bus 2. In this case, the DRAM controller 8 also performs thecoordination of the contention between access to the DRAM through thispath and a refreshing operation.

FIG. 3 is a block diagram showing an internal configuration of the DRAM7. A control signal line 14 to which a control signal for controllingwrite and read is supplied, an address line 15 to which an addresssignal of (A+B) bits is supplied, and a data line 16 to which data issupplied are connected to an input/output interface 17. An address of(A+B) bits is separated by the input/output interface 17 into a rowaddress of A bits and a column address of B bits, of which the rowaddress of A bits is supplied to a row decoder 18 and the column addressof B bits is supplied to a column decoder 19. A memory cell 24 isdisposed in the vicinity of the intersection of the word line 21 and abit line 23. The output of the row decoder 18 is supplied to the wordline 21 selected from a memory cell array 20 and the data in the memorycells on the selected row is output over 2^(B) pieces of the bit lines23. Then, a sense amplifier 22 amplifies the data. Further, the data onthe bit lines selected by the column decoder 19 are output to outsidethe main memory unit 4.

In the description above, the size of the column address is in agreementwith the number of the bit lines and the minimum amount of dataaccessible at one time is one bit. The amount of data accessible at onetime may be either a predetermined value or a value that is to bedetermined each time of access by a signal for specifying the sizeincluded in the control signal 14. Further, the size of the space whichthe column address has may be smaller than the number of bit lines. Inthis case, the minimum amount of data accessible at one time is thevalue obtained by dividing the number of bit lines by the size of thecolumn address space.

Some control methods used in the above described semiconductor circuitwill be described below.

First Embodiment

The basic concept of the control method in the present invention will bedescribed below as compared with the control method in the prior art.

FIG. 4(a) shows the relationship between the stored position of data andthe row when optimization of disposition of data has not been made.Referring to FIG. 4(a), the position indicated by the circle shows theposition in which data is written and an oval indicates an aggregate ofindividual data.

FIG. 4(a) shows an example where the positions to which the data areallocated are randomly determined. In this example, data are written oneach of five rows, which are arranged in succession.

Here in this embodiment, attention is paid to the disposition of data onthe DRAM. With respect to the disposition of the data on the memorycells on each row, when the state of overlapping of the data is examinedin the direction of the bit line 23, there are no overlaps of data onrows 21 a, 21 b, and 21 c and, also, on rows 21 d and 21 e.

Then, the disposition of the data is determined, as shown in FIG. 4(b),so that the number of rows storing data thereon decreases while aplurality of data are disposed so as not to overlap each other on thesame row. The method to determine the combination of the data allocatedto each row with the aim of reducing the number of the rows is solved asa combinatorial optimization problem. In FIG. 4(b), rows 21 a and 21 dto which data are allocated are indicated by thick lines and rows 21 b,21 c, and 21 e to which no data are allocated are indicated by thinlines.

Thus, after having data disposed as described above, setting for thecontrol of execution of the refreshing operation is made for each row.

Each field of the row flag 12 corresponds to each row of the DRAM. TheDRAM controller 8 determines whether refreshing is to be done or not foreach row in accordance with the flag value set in the row flag 12, andperforms the refreshing control for the row which is set to be refreshedby the flag. Each flag of the row flag 12 can be realized by one bit(on/off).

As a method for determining data disposition, there is one performed bya compiler and another performed by an operating system.

In the former method performed by the compiler as shown in FIG. 5, thememory allocation optimization process is applied to the intermediateformat 42 by the memory allocation means 41 as one of the functions ofthe compiler. The process for the combinatorial optimization of data isperformed to minimize the number of rows to which data are actuallyallocated, with the number of rows and the number of memory cells oneach row, as the structure of the memory, used as constraints to therebydetermine relative addresses of individual data. Then, the intermediateformat 43 is output with the operation for setting flags, correspondingto rows on which the data are to be stored, inserted therein. Theintermediate format 43 is converted into a sequence of instructions inthe last step of the compiling process. As a method for actually settingthe flag, there is a method which uses an instruction to automaticallyset/reset the flag for an accessed row, or a method which establishesthe value by an immediate instruction or a data transfer instruction.

In the latter method, performed by the operating system as shown in FIG.6, disposition of pages is determined by the address translation means44, when it maps the pages represented by the virtual address 45 ontothe physical address 46, such that the number of the pages, i.e., thenumber of the rows to which the data are allocated, is minimized. Thesetting of the row flag 12 is realized by incorporating an instructionthat sets the flag as described above, an immediate instruction, or adata transfer instruction, into the address translation means 43 suchthat the flag is set for the row on which data are actually mapped.

After the data have been disposed as described above, refreshingoperations are carried out only for the rows on which the data arestored, whereby unnecessary refreshing operations can be decreased andboth reduction in power consumption and prevention of increase in memoryaccess time due to contention between refresh and memory access can beachieved.

The position in which the compiler or the operating system operates maybe either inside or outside the semiconductor circuit, provided that itis able to know the structure of the memory.

Second Embodiment

Now, a control method in which the disposition of data is determinedtaking note of the lifetime of the data, i.e., the period of time fromfirst writing in of a variable to the reading out thereof at the end.

FIG. 7(a) is a graph showing lifetimes of data A-H to be stored in aDRAM.

If the data are mapped without considering their lifetimes data whoselifetimes are different will be allocated to the same row as shown inFIG. 7(b).

FIG. 7(c) is a drawing in which the lifetimes of the data in FIG. 7(a)are rearranged for each row. Since, for example, row R1 has data B, C,and F stored thereon, it becomes necessary to constantly refresh row R1as long as any of data B, C, and F are live.

Therefore, in the present embodiment, as shown in FIG. 7(d), attentionis paid to the lifetimes of data A-H, and the data are stored so thatthose having lifetimes close to or overlapping each other are disposedon the same row to be stored in the DRAM. The method for determining thecombination of data to be allocated to each row with the aim ofminimizing the sum total of the time periods, during which the live dataare kept stored on each of the rows, is solved as a combinationoptimization problem.

In the example shown in FIG. 7(d), data A and C are disposed on row R0,data B and D on row R1, data F and G on row R2, and data E on row R3.

FIG. 7(e) is a graph showing the lifetimes of the data of each row afterthe positions, in which data A-H are written, have been altered.

Thus, after allocating the data whose lifetimes are overlapping or closeto each other to the same row, the setting for controlling the executionof the refreshing operation is made for each row.

Each field of the row flag 12 is corresponding to each row of the DRAM,and the DRAM controller 8 controls the refreshing operation for therelevant row only during the period set by the flag to indicate that therefreshing operation should be made. Each flag of the row flag 12 isrealized by one bit (on/off).

As a method for determining the data disposition, there is one performedby a compiler and another performed by an operating system.

In the former method, performed by the compiler as shown in FIG. 8, amemory allocation optimization process is applied to the intermediateformat 48 by the memory allocation means 47 as one of the functions ofthe compiler. The memory allocation means 47 obtains the lifetimes ofthe individual data on the basis of a flow graph as the intermediateformat 49. The process for combinational optimization of data isperformed to minimize the sum total for all of the rows of the lifetimesof each of the rows where at least a set of data is still live, with thenumber of rows and the number of memory cells as the structure of thememory used as the constraints, to thereby determine relative address ofindividual data. Then the intermediate format 49 is output with theoperation to set the flag corresponding to the row on which the data isto be stored at the start of the lifetime of the data and the operationfor resetting the flag of the row on which the data is stored at the endof the lifetime of the data inserted therein. The intermediate format 49is converted into a sequence of instructions in the last step of thecompiling process. As a method for actually setting the flag, there is amethod which uses an instruction to automatically set/reset the flag foran accessed row or a method which establishes the value by an immediateinstruction or a data transfer instruction.

In the latter method, performed by the operating system as shown in FIG.9, disposition of pages is determined by the address translation means50, when it maps the pages represented by the virtual address 51 ontothe physical address 52 so that the sum total, for all the rows, of thelifetimes for each of the rows where at least one page is live isminimized, with the number of the rows and the number of the memorycells, as the structure of the memory used as the constraints. Thelifetime of each page is given, when the page includes at least one setof data, by the time period during which the data is live, and it can beobtained by the compiler by analyzing the lifetime of each individualdatum when it allocates the data to each page. The setting of the flagwhen the page is disposed on the physical memory and the resetting ofthe flag when the physical memory is released can be realized byincorporating a flag setting instruction, an immediate instruction, adata transfer instruction, or the like, as described in the firstembodiment, into the address translation means 50.

After the data have been disposed as described above, refreshingoperations are carried out for the rows storing data only for the timeperiod during which the data is live, whereby unnecessary refreshingoperations can be decreased, power consumption reduced, and increase inthe memory access time due to contention between refresh and memoryaccess prevented.

The method of optimization in the temporal domain as described in thesecond embodiment above and the method of optimization in the spatialdomain as described in the first embodiment may be practiced at the sametime.

The compiler or the operating system may work either at inside oroutside the semiconductor circuit provided that it is able to know thestructure of the memory.

Third Embodiment

A control method for determining the disposition of data, with attentionpaid to the data retention time of each of the rows of a DRAM, will bedescribed.

In this example, there is provided, as schematically shown in FIG. 10,the data retention time storing table 9 a storing the data retentiontimes tr0-tr7 on each of a plurality of rows RO-R7 of the DRAM 7.

The storing table 9 a corresponds to the data retention time storingmeans 9 shown in FIG. 1 and can be realized by a device which can bewritten onto such as a PROM, an EPROM, a FLASH memory, or an FPGA. Onthe table 9 a, there is stored, for each row, the data retention time ofthe memory cell which has the shortest data retention time among all ofthe memory cells included in the row.

The measurement of the data retention time is carried out when the DRAMis tested. The results of the measurement are stored on the storingtable 9 a. The information stored in table 9 a, as the data retentiontime may be the time itself, or an encoded value which is divided bysome value.

When the times are divided by rank, an advantage is obtained in that thesize of the table can be decreased.

When data are stored in a main memory unit 4, the data retention timesof each of the rows stored on the storing table 9 a are referred to andthe data are stored in order from the row having the longer dataretention time. Then, the refreshing cycle time adapted to the shortestdata retention time of the row on which data has actually been stored isset in the timer 11.

Upon setting of the timer 11 as described above, setting for controllingthe execution of refreshing is made for each row.

Each field of the row flag 12 corresponds to each row of the DRAM. TheDRAM controller 8 determines whether refreshing is to be made or not foreach row in accordance with the flag value set in the row flag 12 andperforms the control of refreshing of the row which is set by the flagto be refreshed. Each flag of the row flag 12 can be realized by one bit(on/off).

As a method for determining the data disposition, there is one performedby a compiler and another performed by an operating system.

In the former method performed by the compiler as shown in FIG. 11, aprocess of memory allocation optimization is applied to the intermediateformat 54 by the memory allocation means 53 as one of the functions ofthe compiler. When data are allocated to the memory, the values storedon the storing table 9 a are referred to and the physical addresscorresponding to the row having the longer data retention time ispreferentially taken as the object of data allocation, with the numberof rows and the number of memory cells as the structure of the memoryused as the constraints. Then, referring to the data retention time ofthe row which was taken lastly as the object of allocation, the refreshcycle time to be set in the timer 8 is determined. Finally, theintermediate format 55, including the operation to set the flag for therow on which actual data is to be stored and the operation to set therefreshing cycle time, is output. The intermediate format 55 isconverted into a sequence of instructions in the last step of thecompiling process. As a method for actually setting the flag, there aretwo methods. One is to use an instruction to automatically set/reset theflag for an accessed row, the other is to establish the value by animmediate instruction or a data transfer instruction.

In the latter method, performed by the operating system as shown in FIG.12, when a page represented by the virtual address 57 is mapped onto thephysical address 58 by the address translation means 56, the row havingthe longer data retention time is preferentially taken as the object ofallocation of the page, i.e., the data, with the number of rows and thenumber of memory cells on each row as the structure of the memory takenas the constraints. Then, reference is made to the data retention timeof the row lastly taken as the object of allocation and the refreshingcycle time is set in the timer 8 and thus the method can be realized.The setting of the flag and the refreshing cycle time is realized byincorporating an instruction, such as a flag setting instruction, animmediate instruction, or a data transfer instruction, as described inthe first embodiment, into the address translation means 56.

Thus, by using the rows preferentially from those having longer dataretention time, the number of the refreshing operations can bedecreased, power consumption reduced, and increase in the memory accesstime due to contention between refresh and memory access prevented.

It is also possible to use a method for determining the disposition ofdata by taking note of the data retention time of each row as describedin the third embodiment in parallel with the method for optimization inthe spatial domain as described in the first embodiment and the methodfor optimization in the temporal domain as described in the secondembodiment.

The position in which the compiler or the operating system operates maybe either inside or outside the semiconductor circuit provided that itis able to know the structure of the memory.

Fourth Embodiment

A method by which disposition of data, when the data are stored in aDRAM, is determined in accordance with the degree of importance of thedata will be described.

In the data to be stored in the DRAM, there are, for example, those thatcan be corrected for error, such as communication packets, and thosethat cannot be corrected for error.

There are also those data that allow for no error produced therein suchas those for numerical calculation and control purposes, whereas thereare those that cause no serious inconvenience even if some error ispresent therein such as picture/voice data.

Therefore, the rows to store data thereon are determined according tothe degree of importance of the data. Namely, those data which can becorrected for error or those data which allow for some error presenttherein are allocated to rows that have shorter holding times. On theother hand, those data which cannot be corrected for error or those datawhich allow for no numerical error present therein are allocated to suchrows that have longer data retention times. Thus, by disposing dataaccording to the degree of importance of the data thereby suitablyprolonging the cycle time of refreshing, the frequency of the refreshingoperation s can be decreased.

The determination of the disposition of the data according to theirdegree of importance can be achieved, as shown in FIG. 13, by a compilercorresponding to the intermediate format 60 having a function indicativeof the degree of importance of the data. The degree of importance of thedata can be described in a program by for example the provision of typesshowing the degrees of importance. The memory allocation means 59 of thecompiler shown in FIG. 13, making reference to the data retention timeof each row stored in the data retention time storing means 9, disposesdata on the intermediate format 60 in accordance with the degree ofimportance of the data, determines the physical address of individualdata, and outputs the intermediate format 61. The intermediate format 61is converted into a sequence of instructions in the last step of thecompiling process.

The position in which the compiler operates may be either inside oroutside the semiconductor circuit provided that it is able to know thestructure of the memory.

Fifth Embodiment

It is a characteristic of ordinary DRAM that the data retention time ofeach row is not stationary, but variable with the temperature. Namely,as described above, the lower the temperature, the longer the dataretention time. The interval between the refreshing operations of aconventional DRAM is generally set to be very short assuming the worstoperating condition, namely a high-temperature condition. However, sincethe actual data retention time at normal temperatures is great, therefreshing cycle time adapted to the high-temperature condition becomesvery short as compared with the actual data retention time, which meansthat excessive refreshing is then being practiced.

Thus, not only is electric power overly is consumed, but average memoryaccess time increases, because of the more frequent contention occurringbetween refresh and memory access and, thereby, the performance of thelogic portion 33 merged with the DRAM 7 deteriorates.

Therefore, in the embodiment shown in FIG. 14, the semiconductor circuitformed of the DRAM 7 and the logic portion 33 merged on a chip isprovided therein with the temperature detection means 5 for detectingthe temperature of the semiconductor circuit. Thus, by controlling thetimer register 8 a of the DRAM controller 8 according to thetemperature, the refreshing cycle time is suitably set.

The temperature detection means 5 can be realized by a method in which aleakage current of a memory cell having the same temperaturecharacteristic as the memory cell for actually storing data ismonitored, a method in which a ring oscillator is used, or the like(1994. Ito, “VLSI Memory”, Baifukan).

Thus, by setting the refreshing cycle time upon detection of thetemperature, thereby decreasing the frequency of the refreshingoperations, execution of unnecessary refreshing in the DRAM/logic hybridLSI can be decreased and, thereby, both reduction in power consumptionand prevention of increase in the access time due to contention betweenrefresh and memory access can be achieved.

It is also possible to use the method as described in the fifthembodiment, in which the refreshing cycle time is set upon detection ofthe temperature, in parallel with the method of optimization in thespatial domain as described in the first embodiment, the method ofoptimization in the temporal domain as described in the secondembodiment, and the method for determining the disposition of data inaccordance with the data retention time as described in the third andfourth embodiments.

INDUSTRIAL APPLICABILITY

The invention can be utilized in the field of the semiconductor circuitsemploying DRAM.

What is claimed is:
 1. A method of controlling a semiconductor circuitincluding a DRAM comprising the steps of: writing data by determininginterleaved combinations of data, of at least two rows, allocatablerespectively to individual rows so that a number of rows of the DRAMstoring the data thereon is reduced; and selectively refreshing saidrows based on storage of the data thereon.
 2. A method of controlling asemiconductor circuit including a DRAM comprising the steps of: writingdata, having time periods from being written in to being read out, on acommon row of said DRAM based on at least one of overlapping andproximity of the time periods to each other; and refreshing said commonrow only during the time period from the first writing in of the data tothe last reading out thereof.
 3. A method of controlling a semiconductorcircuit including a DRAM comprising the steps of: obtaining a memorycapacity required by an application using said DRAM and writing, inturn, data in said DRAM in an order from a longer data retention timerow to a shorter data retention time row with reference to a tablehaving previously obtained data retention time of each row of said DRAM;and setting a refreshing cycle time on the basis of a row having theshortest data retention time of the rows to which data is stored toreduce the refreshing cycle time.
 4. A method of controlling asemiconductor circuit according to claim 3, wherein the step of writingdata includes writing the data on specific rows in accordance with adegree of importance of the data.
 5. A method of controlling asemiconductor circuit according to claims 1 or 2, further comprising thestep of detecting a temperature of said semiconductor circuit andsetting a refreshing cycle time of said DRAM according to thetemperature.
 6. A semiconductor circuit including a DRAM characterizedby comprising: a unit for writing data so that a number of rows of theDRAM storing data thereon is reduced; and a selective refreshing unitfor selectively refreshing said rows based on storage of the datathereon, whereby rows absent data are not refreshed.
 7. A semiconductorcircuit including a DRAM comprising: a unit for writing data, havingtime periods from being written in to being read out on a common row ofsaid DRAM based on at least one of overlapping and proximity of the timeperiods to each other; and a refreshing unit for refreshing said commonrow only during the time period from the first writing in of the data tothe last reading out thereof.
 8. A semiconductor circuit including aDRAM comprising: a unit for obtaining a memory capacity required by anapplication using said DRAM and writing, in turn, data in said DRAM inan order from a longer data retention time row to a shorter dataretention time row with reference to a table having the previouslyobtained data retention time of each row of said DRAM; and a unit forsetting a refreshing cycle time on the basis of a row having theshortest data retention time of the rows to which data is stored toreduce the refreshing cycle time.
 9. A semiconductor circuit accordingto claim 8, wherein the unit for writing data includes a unit forwriting data on specific rows in accordance with a degree of importanceof the data.
 10. A semiconductor circuit according to claims 6 or 7,further comprising a unit for detecting a temperature of saidsemiconductor circuit and setting a refreshing cycle time of said DRAMaccording to the temperature.